Monitor for timing circuits

ABSTRACT

The input of a pair of gates are connected to a timing circuit, that produces periodic pulses having preset time duration and preset separation, in a manner so that the signals applied to the gates are inverted with respect to the other. One gate is inhibited from responding to the signals for a period of time greater than preset time duration and the other is inhibited for a period of time greater than the preset separation. The gates are connected to a latching circuit so that if the signal applied a gate exceeds its inhibiting period, the latching circuit produces a continuous alarm.

United States Patent [151 3,7Q5,386 Gueldenpfennig et al. 1 Dec. 5, 1972[s41 MONITOR FOR TIMING CIRCUITS 3,313,927 4/1967 Raike et a] ..307/234x [72] lnventors: Klaus Gueldenpiennig, Rochester; ggggigg 3:32: g z' g""228; 2

am e 52:22:; F Z Efi'S Q S S 3,496,546 2/1970 Villafana ..340/171 R xPrimary Examiner-Harold I. Pitts [73] Assignee: Stromberg-CarlsonCorporation, AttorneyCharles Krawczyk Rochester, NY. [22] Filed: April1, 1970 [57] ABSTRACT I The input of a pair of gates are connected to atiming [211 Appl' 24677 circuit, that produces periodic pulses havingpreset time duration and preset separation, in a manner so 5 us Cl 3 7A, 340/167 R, 3 7 B that the signals applied to the gates are invertedwith [511 rm. Cl. ..H04q 1/32 respect to the when one gate is inhibitedfrom 5 Field f Search 340/1 7 171 1 7 A, 167 B; responding to thesignals for a p6l'i0d Of time greater 307/234. 328/109 11 1 than presettime duration and the other is inhibited for a period of time greaterthan the preset separation. [56] References Cited The gates areconnected to a latching circuit so that if I i the signal applied a gateexceeds its inhibiting period, UNITED STATES PATENTS the latchingcircuit produces a continuous alarm.

3,564,285 2/1971 Gilbert ..307/234 13 Claims, 7 Drawing Figures CLOCKRE$ET T t 1 SCANNER l I couursn W DISPLAY DECODER CIRCUIT j i M SCANNERL gmggw g I5 NH 7' L STOP 7 I I3! ig l L! PATENTEDBEB 1912 5 3.705.386

SHEEI 1 OF 3 RESET t ?L :2 .16 I8 SCANNER uomron counr DECODER ERCIRCUIT v DISPLAY SCANNER L 1%Z%TIQR 2| I STOP mman v F I6. I

gi -L64 10 T g.

KLAUS GUEL DE NPF E NNIG EDWARD 6. REEHI L LANSING E. TRYON INVENTORSBYWCWW ATTORNEY PATENTEI] 5 I97? 3. 705, 386

sum 2 OF 3 M Imoa mob :looc IOOn I28) KLAUS GUELOENPFENNIG I26 22 EDWARD6. REEHIL 0N R A Q, umsme E. TRYON CIRCUIT INVENTORS ATTORNEYPATENTEDBEC 51912 SHEET 3 BF 3.

OTHER ALARM CIRCUITS FIG.- 7

KLAUS GUELDENPFENNI6 EDWARD 6. REEHIL LANSING E. TRYON INVENTORSATTORNEY .1 MONITOR FOR TIMING CIRCUITS BACKGROUND OF THE INVENTION Thisinvention pertains to alarm circuits in general,

and more particularly for circuits for monitoring the operation oftiming circuits.

In various electronic systems that are clock controlled to provideproper sequential operation, such as for example, computers andtelephone exchanges, it is very important to continuously monitor theoperation of various timing and sequencing circuits, to detect, as easyas possible, a fault condition, and also to provide an indication as tothe source of the failure. Such timing circuits may exhibit a completefailure, or an erratic failure, such as skipped pulses or as undesirableshifts in time duration.

Timing circuits, such as clock circuits, shift registers or scanners,produce square wave type pulses that al- 2 ternate between high and lowlevels of output, or between different signal polarities. When acircuitof this type fails, it can fail in either state (high or low level) oreither polarity. In order for a monitoring circuit to be effective, itmust be able to detect a failure in either of the states or polarities,and provide an appropriate alarm. In many situations, it is desirablethat the alarm should continue in spite of the fact that the faultcondition has corrected itself, to provide an indication that a faultdid occur at one time. The occurrence of the fault can be acknowledgedand the alarm or monitor circuit reset by persons responsible formaintaining the system.

Monitoring circuits of this type are required to provide a wide varietyof checks throughout entire systems, at various timing rates, and forvarious combinations of symmetrically and/or unsymmetrically timed waveforms. For example, in systems wherein a master clock provides multipletiming outputs at different timing sequences or-rates, it is desirableto monitor each of the timing outputs so that a failure of one can beimmediately detected. In addition, there are occasions when it isnecessary for each of the stages of the shift register or ring counterto be monitored, wherein each of the stages have different switchingsequences. Hence, in order to provide monitoring circuits in a largevariety of locations, such monitoring circuits must be relativelyinexpensive to be economically feasible. Furthermore, it is highlydesirable that a single circuit design will function over a wide rangeof timing conditions and can monitor symmetrical and/or unsymmetricaltimed wave forms, and wherein the circuit can be made to operate underthese various conditions by merely changing component values in themonitoring circuit.

In many timing circuits, such as scanning circuits in telephoneexchanges, the timing circuit is purposely stopped for a presetperiod oftime so that certain functions can be performed. For example, thejunctor and line scanning circuits and their timing circuits are stoppedfor a sufficient period of time for seizing circuits and completingconnections. Once the connections are complete, the scanners arereleased to continue in their timing sequence. A circuit for monitoringthe proper operation of such circuits is required to distinguish betweenan intended break in the timing sequence and a fault condition.

Timing circuits, may at times, have two or more modes of operationwherein the timing sequence changes in each mode of operation. In suchcase, the monitor circuit must have provisions for automaticallyadjusting its operation in accordance with the operating mode in whichthe timing circuit is functioning.

In systems wherein a very large number of timing circuits requireperiodic checks, it may be desirable to have a single monitor circuitthat can be used to periodically scan the operation of the varioustiming circuits on a time divided basis. In such case, the monitorcircuit must have provisions for automatically adjusting the operationof the monitor circuits in accordance with the pulse rate, pulseduration, and pulse separation of the timing circuits of the varioustiming circuits.

It is, therefore, an object of this invention to provide a new andimproved circuit for monitoring the operation of timing circuits.

It is also an object of this invention to provide a new and improvedmonitoring circuit that detects a failure in a timing circuit in eitherstate and/or polarity of failure.

It is still a further object of this invention to provide a new andimproved circuit for monitoring symmetrical and/or unsymmetrical timedwave forms.

It is also an object of this invention to provide a new and improvedmonitoring circuit that is economically feasible for extensive userequiring only component value changes for presetting the timing of thecircuit to proper operation.

It is still a further object of this invention to provide a new andimproved alarm circuit for monitoring the operation of timing circuitsthat provides a continuous alarm condition requiring a reset from theoperator.

It is also an object of this invention to provide a new and improvedcircuit for monitoring the operation of timing circuits that candistinguish between a controlled break in a timing sequence from a faultcondition. 7 I

It is still a further object of this invention to provide a new andimproved circuit for monitoring the operation of timing circuits thathas more than one timing mode of operation.

It is also an object of this invention to provide a new and improvedcircuit for monitoring the operation of timing circuits that cansequentially monitor a large number of timing circuits having differenttiming sequences.

BRIEF DESCRIPTION OF THE INVENTION A circuit for monitoring theoperation of a timing circuit producing periodic pulses having presettime durations and preset spacings therebetween, includes a pair ofsignal translating circuits having their inputs coupled to the timingcircuit so that signals applied to the input circuits are inverted withrespect to each other. One signal translating circuit is inhibited fromresponding to an input signal for a period of time greaterthan thepreset time durations, while the other is inhibited for a period of timegreater than the time corresponding to the preset spacings. An outputcircuit coupled to the translating circuit produces an alarm signal whena signal applied to a translating circuit exceeds the inhibiting period.

A further feature of the invention includes the use of a latchingcircuit as the output circuit to provide a continuous alarm signal.Reset means are produced for resetting the latching circuit.

A still further feature of the invention includes disable means forpreventing the monitor circuit from producing an alarm signal in theevent the operating condition of the timing circuit is intentionallychanged, such as stopped.

Another feature of the invention includes means for automaticallyvarying the inhibit period of the translating circuits so that thecircuit can monitor the operation of a timing circuit whose rate ofoperation is changed and/or can sequentially monitor a large number oftiming circuits.

BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a block diagram of a scanningsystem including the monitor circuit of the invention.

FIG. 2 is a logic diagram of an embodiment of the monitor circuit of theinvention.

FIG. 3 is a schematic diagram of an embodiment of an inhibited signaltranslating circuit for use in the monitor circuit of FIG. 2.

FIG. 4 is a logic diagram of a second embodiment of an inhibited signaltranslating circuit for use in the monitor circuit of the inventionincluding means for automatically controlling the inhibit period of thecircuit in a step-by-step manner.

FIG. 5 is a logic diagram of a third embodiment of an inhibited signaltranslating circuit for use in the monitor circuit of the inventionincluding means for continuously varying the inhibit period of thecircuit.

FIG. 6 is a logic diagram of another embodiment of the monitor of theinvention.

FIG. 7 is a logic diagram of a further embodiment of the monitor circuitof the invention.

THE DESCRIPTION OF THE PREFERRED EMBODIMENT The monitor circuit of theinvention will be explained in conjunction with the telephone scanningsystem of FIG. 1. However, it is to be understood, that the monitorcircuit has application in a large variety of timing systems wherein thetiming circuits provide periodic pulses having preset time durations andpreset spacings therebetween. A clock circuit 10 applies timing pulsesto a counter circuit 12, which, for example, can include a binarycounter. The binary output from the counter 12 is applied to abinary-to-decimal decoder l4 having a plurality of output circuits thatare enabled in sequence, for scanning for a free junctor or a linecircuit (not shown). When a free line orjunctor is located, the countercircuit 12 is stopped by the scanner stop circuit 15 and is held at thiscount until the connections are complete. This type of scanning systemis well known in the art and requires no further explanation.

Binary signals from the counter circuit 12 are also applied to themonitor circuit 16 of the invention, which monitors the operation of thecounter circuit for fault condition. A fault condition can, for example,include an inoperative counter circuit, skipped counts, delayed counts,etc. In the event of a fault, the monitor circuit actuates a visualdisplay device 18. The personnel assigned to the responsibility ofmaintaining this system, can then operate the reset circuit 20, to resetthe monitor circuit to determine if the fault is still present, and ifnecessary, make the required corrections.

Since the telephone counter circuit 12 is stopped when a free linecircuit or a junctor circuit is located, the monitor circuit 16 isdisabled by a signal from the scanner stop circuit 15 so that thecircuit does not produce an alarm signal. In the event that countercircuit 12 includes more than one mode of operation having differenttiming, a monitor inhibit control circuit 21 is used to adjust theinhibit or time out period of the monitor circuit to the mode ofoperation of the counter.

The monitor circuit of FIG. 2 includes a pair of signal translatingcircuits 22 and 24 having an inhibiting circuit for preventing thecircuits from responding to input signals for a preset period of time.In the embodiment of FIG. 2, the translating circuits are illustrated asa pair of NAND gate circuits 22 and 24 having the circuit configurationillustrated in FIG. 3. However, it is to be understood that other typesof circuit arrangements can also be used to provide the function of thedelay or inhibited type insulating circuits. The NAND gate of FIG. 3includes a pair of transistors 26 and 28 connected as a switchingcircuit. The transistor 28 is connected as an output circuit and thetransistor 26 is connected to drive the transistor 28. Input signals tothe gate circuit are applied through the terminals 30 and the diodes 32to the base of the transistor 26. The arrangement is such that athreshold type circuit is present so that when a positive going pulseexceeds a preset certain level, the transistor 28 is switched into asaturated state via the transistor 26.

The response of the circuit to signals at the terminals 30 is inhibitedor delayed by a capacitor 34 connected to the base of the transistor 26.A source of switching or pulse type signals (within the dashed block 36)is illustrated as including a resistor 38 connected between a positivepower terminal 40 and ground through a switching circuit represented bya switch 42. The resistor 38 corresponds to the output impedance of thetiming circuit to be monitored. It can be assumed that the switch 42opens and closes at some periodic rate to switch the terminal 30 betweenground and some high positive level that exceeds the threshold of thecircuit, to produce signal pulses having preset time durations andpreset spacing therebetween. Without the capacitor 34, the transistors26 and 28 would immediately respond to the signals, to produce an outputsignal. The capacitor 34 acts as a charging circuit providing a timedelay circuit. The time delay is determined by the charging path for thecapacitor 34 and the circuit threshold level. The time delay circuitprevents the base of the transistor 26 from reaching the circuitthreshold level for a period of time greater than the proper timeduration of the pulse to be monitored, and, in effect, inhibits theresponse of the circuit to properly timed pulses.

A flip-flop circuit 50 is included in FIG. 2 to represent a stage of atiming circuit, such as a stage of Qe binary counter of the countercircuit 12. The Q and Q outputs of the flip-flop 50 are connected to theinputs of the gates 22 and 24 respectively so that the pulmsnno nus sesapplied to the gates are inverted with respect to each other. The sizeof the capacitors 56 and 58 (corresponding to the capacitor 34 of FIG.3) are selected so that therespective gate circuits are inhibited fromresponding to the input pulses for a period of time greater than theproper time duration of the pulses to be applied thereto. In the eventthat the flip-flop is switched from state to state for equal periods oftime, the pulses on lines 52 and 54 will be of equal duration and equalspacing. In such' case, the values of the capacitors 56 and 58 will beequal. In the event that the operation of the flip-flop is such that itproduces unsymmetrical pulses, i.e. the pulse on and off periods areunequal, the size of the capacitors 56 and 58 are adjusted accordinglyto provide the correct value of inhibiting delay. In the event only asingle output signal is monitored, such as that of line 52, an inverter60 is connected to apply inverted pulses from line 52 to the gate 24.

The arrangement is such that a failure in the timing sequence of theflip-flop 50 in either of its stable states will be detected. A failureto switch the flip-flop 50 within the designated time will apply a highlevel signal to one of the gates 22 and 24 via the lines 52 and 54, orin the event of a single output, via line 52 and the inverter 60, thatexceeds the inhibit period of one of the gate circuits. A failure of theflip-flop in either of its stable states of operation is thereforedetected. In addition, in case of a single output, a failure in the highor low level state is also detected.

The presence of the high level signal having a time duration greaterthan the inhibit delay at one of the gates 22 and 24 results in thetransmission of an alarm signal from the gate to a NOR gate 62. Inresponse to the alarm signal, the NOR gate applies a high level signalto an input of NAND gate 64. Under normal operation, the NAND gate 64 ispartially enabled via a reset circuit including a resistor 66, and alsois partially enabled by a signal on terminal 68 and, therefore, respondsto the alarm signal to energize a relay 70. When the relay 70 isenergized, the normally open relay contacts 72 close to energize analarm light 74, and the normally closed relay contacts 76 open so that ahigh level signal from resistor 77 is applied to a NAND gate 78. Theoutput from the NAND gate 78, in turn, applies a latching signal to theNQR gate 62 maintaining the relay 70 energized, thus providing acontinuous alarm signal. The maintenance personnel will acknowledge-thealarm signal by depressing a reset push button 80, which in turn, causesthe NAND gate 64 to de-energize the relay 70 and reset the circuit. Inthe event the problem causing the alarm condition has not beencorrected, the circuit will again latch into the alarm condition. Whenthe monitor circuit of the invention is used for monitoring a scanner ora counter circuit that is purposely stopped, a disable signal is appliedto the terminal 68 that prevents the NAND gate 64 from responding to thealarm signal.

FIGS. 4 and 5 include embodiments of inhibited signal translatingcircuits that can be substituted for the NAND gates 22 and 24 (and theirrespective capacitors 56 and 58) in the circuit of FIG. 2, and NANDgates 150 and 152 (and their respective capacitors 160 and 162) in thecircuit of. FIGS. 6 and 7. I

The embodiment of the inhibited signal translating circuit of FIG. 4includes a plural input NAND gate 98 having a variable inhibitingcircuit for changing the inhibit period of the translating circuit in astep-wise fashion. The circuit of FIG. 4 includes a plurality ofcapacitors 100a, 100b, l00c-l00n that function as the capacitor 34 ofFIG. 3, when switched into operation. The capacitors 100a-100n areconnected in series with the diodes 102a-l02n, respectively. The otherends of the diodes l02a-102n are connected to a biasing circuit,including a resistor 104 connected in series with a zener diode 106between a power terminal 108 and ground. The biasing circuit provides areverse bias to the diodes l02a-102n that normally maintains the diodesin a cut-off condition and thereby open-circuiting their respectivecapacitors.

A plurality of NAND gates lllla-llOn are connected through individualresistors l12a-112n to one end of the capacitors l00a-100n,respectively. The arrangement is such that the capacitors l00a-lltl0nare effectively open circuited until its associated NAND gate 11012-1 Inis enabled. When a NAND gate is enabled, the connection between itsassociated capacitor and diode is grounded, thereby completing thecircuit for that particular capacitor to function as the inhibitingcircuit. As can be seen, the inhibit period of the circuit can bechanged in a step-wise fashion by enabling individual ones of the gatesIIOa-lllfln, or enabling groups of the gates, thereby controlling thevalue of the capacitance connected for operation in the inhibit circuit.

The monitor circuit can function to monitor a plurality of timingcircuits by receiving the input signals to be monitored at one of theinput circuits of the NAND gate 98 and enabling the proper NAND gate1l0a-110 n to provide the corresponding inhibiting period. During thetime the monitor circuit is switched from one timing circuit to another,the NAND gate 64 of FIG. 2 will be disabled for a sufficient period oftime to allow the switch over to be completed.

The embodiment of the signal translating circuit of FIG. 5 includes aNAND gate having a continuously variable inhibit circuit. In FIG. 5, thecapacitor 34!- of FIG. 3 is replaced by a combination of a capacitor 122connected in series with a varactor 124, connected to a positive inputreference potential. The varactor is a voltage variable capacitor, forexample, of the type specified in the Semiconductor Data Book, publishedby Motorola Semiconductor Products, Inc., Fourth Edition, June 1969, onPage AN-75 through AN-79. The junction of the capacitor 122 and thevaractor 124 is coupled through a resistor 126 to a control circuit 128.The control circuit functions to provide a predetermined potential tocontrol the capacitive value of the varactor 124. The control circuit128 can, for example, be a gated direct current amplifier for applyingcontrolled DC potentials in response to switching signals. The inhibitperiod of the circuit of FIG. 5 will depend upon the capacitance valueof the series combination including the capacitor 122 and the varactor124.

The circuits of FIGS. 4 and 5 provide a variable inhibit arrangement sothat a single monitor circuit of the invention can monitor a pluralityof different timing circuits on a time sharing basis and/or monitor atiming circuit that has more than one timing mode of operation.

In the embodiment of FIGS. 6 and 7, the inhibited signal translatingcircuits are disabled during the period the monitor circuit is to benon-responsive to timing signals. In FIG. 6, the inhibited translatingcircuits comprise a pair of NAND gates 150 and 152 and their connectedcapacitors 160 and 162, each comprising a circuit of the typeillustrated in FIG. 3. Input signals from the terminals 154 and 156 areapplied to the NAND gates 150 and 152 in a manner so that the signalsare inverted with respect to each other. In the event a single timingsignal is monitored, the NAND gate 158 (shown in dotted lines) isconnected between the input circuits ofthe NAND gates.

The capacitors 160 and 162 are connected to the NAND gates 150 and 152in the same manner as the capacitor 34 of FIG. 3 to provide theinhibiting time delay. A relay 164 is connected between a positive powersupply terminal 166 and the output circuits of the NAND gates 150 and152 so that the relay is energized whenever a signal applied to one ofthe terminals 154 and 156 exceeds the inhibiting time period of theconnected NAND gates. A contact 168 of the relay 164 is connectedbetween ground and one end of the relay through a reset push button 170to latch in the relay and thereby provide continuous alarm signal. Asecond relay contact 172, when closed, energizes the alarm light 174.The circuit of FIG. 6 is reset by depressing the push button 170 whichopen circuits the relay latching circuit. In the event the alarm signalis still present, the relay 164 will continue to be energized.

A second input of each of the NAND gates 152 and 154 is connected to adisable terminal 176, which can be, for example, one of the unconnectedterminals 30 of FIG. 3. In the event the input signals to the circuit ofFIG. 6 are stopped, such as in the case of the scanning system of FIG.I, a ground or low disable signal is applied to the terminal 176 toprevent the NAND gates from responding to input signals for the durationof the disable signal.

The circuit of FIG. 7 is similar to that of FIG. 6, however, includingan electronic latching circuit. In FIG. 7, the output of the NAND gatesare connected to an alarm light 180 so that the light is energizedwhenever the signal applied to one of the NAND gates 150 and 152 exceedsits inhibiting period. The output of the NAND gates 150 and 152 are alsoapplied to a latching circuit 185 which includes a pair of NAND gates182 and 184 connected as a bi-stable flip-flop circuit. An alarm signalfrom either of the NAND gates 150 or 152 will set the latching circuitso that a continuous low or ground signal be applied to the alarm light180 via line 187. The latching circuit is reset by depressinga resetpush button 186 which removes a positive enable signal from a resistor189 and applies ground to an input of the NAND gate 164, which resetsthe latching circuit, provided the alarm condition has been corrected. Athird input circuit of the NAND gate 184 is connected to an inputterminal 188 and can function as an alternative disable circuit forpreventing the latching circuit from being set during the time themonitor circuit is to be non-responsive to input timing signals.

What is claimed is:

1. A timing and monitor circuit comprising:

timing means for producing periodic output pulses having preset timedurations and preset spacings therebetween;

first and second delay circuits, the first delay circuit exhibiting atime delay greater than said preset time duration, and said second delaycircuit exhibiting a time delay greater than the period of timecorresponding to said preset spacings, each of said delay circuits beingresponsive to input signals having a time duration greater than its timedelay for producing output signals; circuit means coupling said firstand second time delay circuits to said timing means so that the pulsesapplied to said second delay circuit are inverted with respect to thoseapplied to said first delay circuit;

a latching circuit coupled to said first and second delay circuits forproducing a continuous alarm signal in response to an output signal fromsaid delay circuits, and

circuit means for resetting said latching circuit.

2. A circuit as defined in claim 1 including:

disable means for disabling said monitor circuit from responding totiming pulses.

3. A circuit as defined in claim 1 including:

circuit means coupled to said delay circuit for adjusting said timedelays.

4. A timing and monitor circuit comprising:

timing means for producing periodic pulses having preset time durationsand preset spacings therebetween;

a pair of signal translating circuits;

circuit means coupling said timing means to the inputs of saidtranslating circuits so that the signals applied to the inputs of saidtranslating circuits are inverted with respect to each other;

circuit means coupled to one of said translating circuits for inhibitingsaid circuit from producing an output signal in response to an inputsignal for at least said preset time duration;

circuit means coupled to the other one of said translating circuits forinhibiting said circuit from producing an output signal in response toan input signal for at least a period corresponding to said presetspacings, and

circuit means coupled to the output of said pair of translating circuitsfor producing an alarm signal in response to an output signal from saidtranslating circuits.

5. A circuit as defined in claim 4 wherein:

said circuit means coupled to the output of said translating circuitscomprises a latching circuit for providing a continuous signal inresponse to an output signal from said translating circuits, and

circuit means for resetting said latching circuit.

6. A circuit as defined in claim 4 wherein:

said translating circuits comprise gate circuits, and

said inhibiting circuit means coupled to said translating circuitsincludes capacitive means providing a charging circuit for delaying theresponse of the gate circuits to the input signals.

7. A circuit as defined in claim 4 wherein:

said timing means provides a pair of output signals wherein one signalis the inverse of the other, and

said circuit means coupling said timing means to said translatingcircuits couples individual ones of said pair of output signals toseparate inputs of said translating circuits.

v 8. A circuit as defined in claim 4 wherein:

said circuit means coupling said timing means to said translatingcircuit applies said periodic pulses to one of said translating-circuitsand inverts said periodic pulses prior to applying them to said othertranslating circuit.

9. A circuit for monitoring the operation of a timing circuit producingperiodic pulses having preset time durations and preset spacingstherebetween comprisingz v a pair of signal translating circuits;

circuit means coupling the timing circuit to the inputs of saidtranslating circuits so that the signals applied to the inputs of saidtranslating circuits are inverted with respect to each other;

capacitive means for providing a charging circuit coupled to one of saidtranslating circuits for inhibiting said circuit from producing anoutput signal in response to an input signal for at least said presettime duration;

capacitive means for providing a charging circuit coupled to the otherone of said translating circuits for inhibiting said circuit fromproducing an output signal in response to an input signal for at least aperiod corresponding to said preset spacings;

circuit means for adjusting the values of said capacitive means, and Vcircuit means coupled to the output of said pair of translating circuitsfor producing an alarm signal in response to an output signal from saidtranslating circuits.

10. A circuit as defined in claim 9 wherein:

said capacitive means includes a plurality of capacitors, and

said control circuit means includes means for selecting at least one ofsaid capacitors to control the duration of said inhibit period.

1 l. A circuit as defined in claim 9 wherein:

said capacitive means is electrically variable, and

said control circuit means controls the value of said capacitive means.

12. A circuit as defined in claim 9 including:

a disable circuit for selectively disabling said monitor circuit fromresponding to the timing signals.

13. A circuit for monitoring the operation of a timing circuit producingperiodic pulses having preset time durations and preset spacingstherebetween comprising:

a pair of signal translating circuits;

circuit means coupling the timing circuit to the ina eriod corres ondinto said resets acin s and circ it means co pled t?) the ou put of saidaair of translating circuits for producing a signal in response to anoutput signal from said translating circuits.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO.3,705,386

DATED December 5, 1972 INVENTOR(5) I Klaus Gueldenpfennig, et al.

It is certified that error appears in the above-identified patent andthat said Letters Patent Q are hereby corrected as shown below:

Col. L, line 26 "insulating" should read 9 -translating-.

Col. 8, line 11 "circuit means" should begin a new paragraph.

Engned and Sealed this twenty-eight Day Of October 1975 E O Arrest:

RUTH C. MiSON C. MARSHALL DANN Q Arres-tmg ()jjrcer Commissioneruj'Parenrs and Trademarks

1. A timing and monitor circuit comprising: timing means for producingperiodic output pulses having preset time durations and preset spacingstherebetween; first and second delay circuits, the first delay circuitexhibiting a time delay greater than said preset time duration, and saidsecond delay circuit exhibiting a time delay greater than the period oftime corresponding to said preset spacings, each of said delay circuitsbeing responsive to input signals having a time duration greater thanits time delay for producing output signals; circuit means coupling saidfirst and second time delay circuits to said timing means so that thepulses applied to said second delay circuit are inverted with respect tothose applied to said first delay circuit; a latching circuit coupled tosaid first and second delay circuits for producing a continuous alarmsignal in response to an output signal from said delay circuits, andcircuit means for resetting said latching circuit.
 2. A circuit asdefined in claim 1 including: disable means for disabling said monitorcircuit from responding to timing pulses.
 3. A circuit as defined inclaim 1 including: circuit means coupled to said delay circuit foradjusting said time delays.
 4. A timing and monitor circuit comprising:timing means for producing periodic pulses having preset time durationsand preset spacings therebetween; a pair of signal translating circuits;circuit means coupling said timing means to the inputs of saidtranslating circuits so that the signals applied to the inputs of saidtranslating circuits are inverted with respect to each other; circuitmeans coupled to one of said translating circuits for inhibiting saidcircuit from producing an output signal in response to an input signalfor at least said preset time duration; circuit means coupled to theother one of said translating circuits for inhibiting said circuit fromproducing an output signal in response to an input signal for at least aperiod corresponding to said preset spacings, and circuit means coupledto the output of said pair of translating circuits for producing analarm signal in response to an output signal from said translatingcircuits.
 5. A circuit as defined in claim 4 wherein: said circuit meanscoupled to the output of said translating circuits comprises a latchingcircuit for providing a continuous signal in response to an outputsignal from said translating circuits, and circuit means for resettingsaid latching circuit.
 6. A circuit as defined in claim 4 wherein: saidtranslating circuits comprise gate circuits, and said inhibiting circuitmeans coupled to said translating circuits includes capacitive meansproviding a charging circuit for delaying the response of the gatecircuits to the input signals.
 7. A circuit as defined in claim 4wherein: said timing means provides a pair of output signals wherein onesignal is the inverse of the other, and said circuit means coupling saidtiming means to said translating circuits couples individual ones ofsaid pair of output signals to separate inputs of said translatingcircuits.
 8. A circuit as defined in claim 4 wherein: said circuit meanscoupling said timing means to said translating circuit applies saidPeriodic pulses to one of said translating circuits and inverts saidperiodic pulses prior to applying them to said other translatingcircuit.
 9. A circuit for monitoring the operation of a timing circuitproducing periodic pulses having preset time durations and presetspacings therebetween comprising: a pair of signal translating circuits;circuit means coupling the timing circuit to the inputs of saidtranslating circuits so that the signals applied to the inputs of saidtranslating circuits are inverted with respect to each other; capacitivemeans for providing a charging circuit coupled to one of saidtranslating circuits for inhibiting said circuit from producing anoutput signal in response to an input signal for at least said presettime duration; capacitive means for providing a charging circuit coupledto the other one of said translating circuits for inhibiting saidcircuit from producing an output signal in response to an input signalfor at least a period corresponding to said preset spacings; circuitmeans for adjusting the values of said capacitive means, and circuitmeans coupled to the output of said pair of translating circuits forproducing an alarm signal in response to an output signal from saidtranslating circuits.
 10. A circuit as defined in claim 9 wherein: saidcapacitive means includes a plurality of capacitors, and said controlcircuit means includes means for selecting at least one of saidcapacitors to control the duration of said inhibit period.
 11. A circuitas defined in claim 9 wherein: said capacitive means is electricallyvariable, and said control circuit means controls the value of saidcapacitive means.
 12. A circuit as defined in claim 9 including: adisable circuit for selectively disabling said monitor circuit fromresponding to the timing signals.
 13. A circuit for monitoring theoperation of a timing circuit producing periodic pulses having presettime durations and preset spacings therebetween comprising: a pair ofsignal translating circuits; circuit means coupling the timing circuitto the inputs of said translating circuits so that the signals appliedto the inputs of said translating circuits are inverted with respect toeach other; capacitive means for providing a charging circuit coupled toone of said translating circuits for inhibiting said circuit fromproducing an output signal in response to an input signal for at leastsaid preset time duration; capacitive means for providing a chargingcircuit coupled to the other one of said translating circuits forinhibiting said circuit from producing an output signal in response toan input signal for at least a period corresponding to said presetspacings, and circuit means coupled to the output of said pair oftranslating circuits for producing a signal in response to an outputsignal from said translating circuits.